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Parallel without the Pain™

THE PAIN

Since the 1980s, HPC (High Performance Computing) explored and established the techniques needed to wield parallel computation—computing using many processors at the same time—to solve ever larger computational problems. Although HPC has reaped benefits for its industry and the most technically advanced parts of academia, the sciences, and government, it has failed, after many attempts, to carry its benefits to the mainstream software industry and non-expert programmers. A UC Berkeley publication stated: “Experience teaching parallelism suggests that not every programmer is able to understand the nitty gritty of concurrent software and parallel hardware.” (Krste Asanovic et al. - “A View of the Parallel Computing Landscape” article, UC Berkeley ParLab, October 2009).

This separation mattered little before the 21st century, because mainstream computers had only a single processor in them, but today virtually all new computers have multiple computing cores. With the advent of multicores in desktop and laptop computing, tablets and mobile phones, a gap between the theoretical computing capability of computing hardware and the performance achieved by its software is growing exponentially. By 2012, it is well known that the average industry software writer cannot efficiently use computational power beyond one processor’s core.

The software industry cannot ignore this situation much longer. Desktop hardware has 24 virtual cores, and CPU manufacturers like Intel and AMD are experimenting with 80 cores per chip and more. Likewise, hardware manufacturers in HPC would like to grow their audience beyond their traditional HPC industry, so they need a way to make it practical for more software to run on their hardware.

THE SOLUTION - ACS’S SET™

(Supercomputing Engine Technology™)

SET provides a way for average software writers to continue “thinking” in serial (i.e., continue writing for a single processor), yet with a minimum of glue code (i.e., code that does not change the program’s functionality), utilize parallel computing in the most successful way found in HPC. Application writers with a well-organized, modular code already take advantage of the clear organization of serial implementations of computations that is vital not only to code maintenance but also to any parallel computing technique. Because the application writers understand the nature of their code, particularly its data management needs, those writers are best suited to determine which parts of SET to apply to their code, to enable a full-fledged parallelized application.

SET does not compete with the most advanced experts of HPC, who will continue to write the most advanced HPC implementations and scale to the largest HPC hardware. Despite how well the experts scale codes, such expertise is limited to a select few programmers. The typical software writer cannot be expected to learn these elite techniques. On the other hand, SET implements parallel computing like that of the experts, but using SET requires only a basic understanding beyond serial programming. That capability of SET is what enables the average application programmer to wield the power of parallel computing.

Watch a short SET™ Introduction movie.

See our Products pages for more information on this breakthrough patented technology.

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“...So what used to be quite an obscure programming problem for supercomputers and academics, which is how do you reliably and efficiently take advantage of massively-powered computers is starting to become a real problem on the desktop because if software doesn’t take advantage of these cores then Intel could go on pushing out chips that have more and more processing cores inside them but the software won’t be getting any faster, we’ll have this growing gap between what my computer’s theoretically capable of and what it actually does.”

A quote from The Economist Babbage Podcast - May 18, 2011 - The Economist magazine's Babbage weekly podcast about science and technology discusses Gordon Moore's Law in light of the latest advances in three-dimensional chip construction.

( News )